integrated circuit systems, inc. general description features av 917 3 - 01 block diagram video genlock pll av9173-01revc052197p ? phase-detector/vco circuit block ? ideal for genlock system ? reference clock range 25 khz to 1 mhz for full output clock range ? input clocks down to 12 khz possible with restricted output conditions (see table 1) ? output clock range 1.25 to 75 mhz ? on-chip loop filter ? single 5 volt power supply ? low power cmos technology ? small 8-pin dip or soic package the av9173-01 provides the analog circuit blocks required for implementing a video genlock dot (pixel) clock generator. it contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (vco). by grouping these critical analog blocks into one ic and utilizing external digital functions, performance and design flexibility are optimized as are development time and system cost. when used with an external clock divider, the av9173-01 forms a phase-locked loop configured as a frequency synthesizer. the av9173-01 is designed to accept video horizontal synchronization (h-sync) pulses and produce a video dot clock. a separated, negative-going sync input reference pulse is required at pin 2 (i n). the av9173-01 is also suited for other clock recovery applications in such areas as data communications. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 av9173-01 pin descriptions pin configuration 8-pin dip or soic table 1: allowable input frequency to output frequency (outputs in mhz) pin number pin name type description 1 fbin input feedback input 2 in input input for reference sync pulse 3 gnd ground 4 fs0 input frequency select 0 input 5 oe input output enable 6 clk1 output clock output 1 7 vdd power supply (+5v) 8 clk2 output clock output 2 (divided-by-2 from clock 1) f in (khz) f out for fs = 0 (mhz) f out for fs = 1 (mhz) clk1 output clk2 output clk1 output clk2 output 12 f in 14 khz 44.0 to 75 22.0 to 37.5 11.0 to 18.75 5.5 to 9.375 14 < f in 17 khz 30.0 to 75 15.0 to 37.5 7.5 to 18.75 3.75 to 9.375 17 < f in 30 khz 25.0 to 75 12.5 to 37.5 6.25 to 18.75 3.125 to 9.375 30 < f in 35 khz 15.0 to 75 7.5 to 37.5 3.75 to 18.75 1.875 to 9.375 35 < f in 1000 khz 10.0 to 75 5.0 to 37.5 2.5 to 18.75 1.25 to 9.375
3 av9173-01 using the av9173-01 figure 1: typical application of av9173-01 in a video genlock system most video sources, such as video cameras, are asynchronous, free-running devices. to digitize video or synchronize one video source to another free-running reference video source, a video genlock (generator lock) circuit is required. the av9173-01 integrates the analog blocks which make the task much easier. in the complete video genlock circuit, the primary function of the av9173-01 is to provide the analog circuitry required to generate the video dot clock within a pll. this application is illustrated in figure 1. the input reference signal for this circuit is the horizontal synchronization (h-sync) signal. if a composite video reference source is being used, the h-sync pulses must be separated from the composite signal. a video sync separator circuit, such as the national semiconductor lm1881, can be used for this purpose. the clock feedback divider shown in figure 1 is a digital divider used within the pll to multiply the reference frequency. its divide ratio establishes how many video dot clock cycles occur per h-sync pulse. for example, if 880 pixel clocks are desired per h-sync pulse, then the divider ratio is set to 880. hence, together the h-sync frequency and external divider ratio establish the dot clock frequency: f out = f in ? n where n is external divide ratio both av9173-01 input pins in and fbin respond only to negative-going clock edges of the input signal. the h-sync signal must be constant frequency in the 25 khz to 1 mhz range and stable (low clock jitter) for creation of a stable output clock. refer to application brief (ab01) for additional details on use of input frequencies below 25khz. by following the guidelines in this brief and meeting the test conditions in the ac specifications (vco frequency), an input as low as 12khz (such as ntsc or pal h-sync) can be used. the output hook-up of the av9173-01 is dictated by the desired dot clock frequency. the primary consideration is the internal vco which operates over a frequency range of 10 mhz to 75 mhz. because of the selectable vco output divider and the additional divider on output clk2, four distinct output frequency ranges can be achieved. the following table lists these ranges and the corresponding device configuration. note that both outputs, clk1 and clk2, are available during operation even though only one is fed back via the external clock divider. pin 5, oe, tristates both clk1 and clk2 upon logic low input. this feature can be used to revert dot clock control to the system clock when not in genlock mode (hence, when in genlock mode the system dot clock must be tristated). when unused, inputs fs0 and oe must be tied to either gnd (logic low) or vdd (logic high). for further discussion of vco/pll operation as it applies to the av9173-01 , please refer to the av9170 application note. the av9170 is a similar device with fixed feedback dividers for skew control applications. fs0 state output used frequency range 0 0 1 1 clk1 clk2 clk1 clk2 10 - 75 mhz 5 - 37.5 mhz 2.5 - 18.75 mhz 1.25 - 9.375 mhz
4 av9173-01 absolute maximum ratings v dd (referenced to gnd) . . . . . . . . . . . . . . . . 7.0 v operating temperature under bias . . . . . . . . . 0 c to + 70 c storage temperature . . . . . . . . . . . . . . . . . . . . C 65c to + 150c voltage on i/o pins referenced to gnd . . . . . gnd C 0.5 v to v dd + 0.5 v power dissipation . . . . . . . . . . . . . . . . . . . . . . 0.5 watts stresses above those listed under absolute maximum ratings above may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. v dd = + 5v 5%, t a = 0c to 70c, unless otherwise stated electrical characteristic notes: 1. duty cycle measured at 1.4v. 2. input reference frequency = 25 khz, output frequency = 25 mhz. jitter measured between adjacent vertical pixels. 3. clk1 frequency applies for fs = 0. for fs = 1 condition, divide allowable clk1 range by the factor of 4. dc characteristics parameter symbol test conditions min typ max units input low voltage v il v dd = 5v 0.8 v input high voltage v ih v dd = 5v 2.0 v input low current i il v in = 0v - 5a input high current i ih v in = v dd - 55 a output low voltage 1 v ol i ol = 8ma 0.4 v output high voltage 1 v oh1 i oh = -1ma, v dd = 5.0v v dd -0.4v v output high voltage 1 v oh2 i oh = -4ma, v dd = 5.0v v dd -0.8v v output high voltage 1 v oh3 i oh = -8ma 2.4 v supply current i dd unloaded, 50 mhz 20 50 ma
5 av9173-01 v dd = + 5v 5%, t a = 0c to 70c, unless otherwise stated electrical characteristics notes: 1. parameter is guaranteed by design and characterization. not 100% tested in production. 2. input reference frequency = 25 khz, output frequency = 25 mhz. jitter measured between adjacent vertical pixels. 3. clk1 frequency applies for fs = 0. for fs = 1 condition, divide allowable clk1 range by the factor of 4. 4. an application brief (ab01) documents the operation of the av9173 for low input frequencies. this provides guidelines for usable output frequencies and feedback ratios required to use inputs below 25 khz. by following these guidelines, the av9173 will operate down to 12 khz inputs across temperature, voltage and lot-to-lot variation. ac characteristics parameter symbol test conditions min typ max units input clock rise time 1 iclk r 10 ns input clock fall time 1 iclk f 10 ns output rise time 1 t r1 15pf load; 0.8 to 2.0v 0.6 1.5 ns output rise time 1 t r2 15pf load; 20% to 80% v dd 1.6 3.0 ns output fall time 1 t f1 15pf load; 2.0 to 0.8v 1.0 2.0 ns output fall time 1 t f2 15pf load; 80% to 20% v dd 0.9 2.0 ns output duty cycle 1 d t 15pf load 40 47 55 % jitter, one sigma 1 t 1s1 clk1 frequency 3 25 mhz 120 250 ps jitter, absolute 1 t abs1 clk1 frequency 3 25 mhz -400 250 400 ps jitter, one sigma 1 t 1s2 clk1 frequency < 25 mhz 1 % jitter, absolute 1 t abs2 clk1 frequency < 25 mhz 2 % line-to-line jitter, 1 absolute 2 tl abs 4ns input frequency, 1 in or fbin f i see allowable f i below: 12 1000 khz clk1 frequency 1, 3, 4 f clk1 12 f i 14 khz 44.0 75 mhz 14 < f i 17 khz 30.0 75 mhz 17 < f i 30 khz 25.0 75 mhz 30 < f i 35 khz 15.0 75 mhz 35 < f i 1000 khz 10.0 75 mhz
6 av9173-01 ordering information av9173-01cn08 - or - av9173-01cs08 8-pin dip package 8-pin soic package xxx xxxx - ppp m x#w lead count & package width lead count = 1, 2 or 3 digits w = 0.3" soic or 0.6" dip; none = standard width package type n = dip (plastic) s = soic pattern number (2 or 3 digit number for parts with rom code patterns) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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